Controlling on-screen displays

ABSTRACT

Apparatus for controlling synchronization of on-screen display information in an auto-search mode of a radio-frequency receiver ( 2 ) connected to scan an incoming signal for valid channel frequencies. The apparatus comprises: a picture intermediate frequency phase-locked loop detector ( 17 ) for supplying an output signal indicating whether an intermediate frequency demodulator is in an unlocked mode which is the case if the incoming signal frequency does not correspond to a valid channel frequency, or in a locked mode, which is the case if the incoming signal frequency does correspond to a valid channel frequency; a video detector ( 18 ) for detecting a video property in the incoming signal, a synchronization phase control loop ( 6, 8, 10 ) which is closed if the video property is detected and the output signal indicates the locked mode, a memory for storing the frequency of the incoming signal as a valid channel when the phase control loop ( 6, 8, 10 ) is closed and a horizontal oscillator ( 8 ) connected to free run when the phase control loop ( 6, 8, 10 ) is open. This stabilizes an on-screen display even when no signal is present or a weak signal is present.

[0001] The present invention relates to on-screen displays, particularly such displays as are commonly used on the picture screen when a television tuner is in the auto-search mode.

[0002] An On-screen display (OSD) typically comprises alphanumeric and/or picture characters to provide information to the user, for example, regarding channel number, programming choices, and prompting statements. Typically, the OSD signals are supplied to the luminance/chrorninance processing part of the television receiver to be displayed on the screen superimposed on any picture signal received by the tuner. To ensure that the OSD always appears in the same position on the screen, it is synchronized with the horizontal and vertical deflection timing pulses which are separated in the receiver from the received television signal.

[0003] A problem arises when an OSD is required at a time when no picture signal is being received, for example during tuning, or if the picture signal is weak. Then either no timing pulses are present or the timing pulses are very noisy because of residual harmonics which appear as false video synchronizing signals at the output of the picture intermediate frequency demodulator (further referred to as “PIF demodulator”) which demodulates the intermediate frequency supplied by a tuner into a baseband video signal. This tends to produce disturbances and distortion in the OSD, including jagged edges and vertical bounce because the position of the OSD characters will tend to vary from line to line and from field to field. This is evidently undesirable. The problem is particularly acute during an auto search tuning mode of a television receiver.

[0004] It has been proposed to use a substitute synchronizing signal in circumstances when no suitable external signal is being received. This increases the cost of the receiver. Alternatively, U.S. Pat. No. 4,677,484 proposes a dedicated deflection signal source and control means to switch the source from an operating mode, in which it is synchronized with a received synchronizing signal, to a mode in which it is free running, when the incoming signal is determined to have an invalid or unsuitable synchronizing signal. This again requires expensive additional circuitry.

[0005] It is an object of the invention to provide an on-screen display which obviates the above-mentioned problems. The invention is defined by the independent claims. The dependent claims define advantageous embodiments.

[0006] There is preferably also a coincidence detector to verify the coincidence detection status to confirm the presence of a valid channel frequency indicating a real transmission.

[0007] According to a preferred embodiment, the video property is a line frequency signal and the memory may be non-volatile.

[0008] According to a second aspect of the present invention, a method is provided for controlling synchronization of on-screen display information in the auto-search mode of a radio-frequency receiver connected to scan an incoming signal for valid channel frequencies, the method comprising the steps of:

[0009] a) initiating a channel frequency search mode;

[0010] b) opening a synchronization phase control loop and setting a horizontal oscillator to free run, for example, by switching a vertical divider in the auto mode;

[0011] c) generating on-screen display information, preferably for a full screen;

[0012] d) scanning an incoming signal for valid channel frequencies;

[0013] e) monitoring the incoming signal for the presence of a video property;

[0014] f) if the video property is detected, causing the program to wait only for a predetermined time; if the video property is not detected proceed to step j);

[0015] g) checking the lock status of the PIF phase-locked loop;

[0016] h) closing the synchronization phase control loop only if the PIF phase locked loop is locked (or more general, if the PIF demodulator does not comprise a phase locked loop, when a detector coupled to the PIF demodulator detects a locked state indicating that it is very likely that a valid channel frequency is detected);

[0017] i) then storing the data if the PIF phase locked loop is locked and the video property is present;

[0018] i) seeking the next channel and proceeding with step b) as long as not all channels have been searched.

[0019] The channel frequency data is preferably stored in a non-volatile memory and the video property is preferably a line frequency signal.

[0020] The accuracy of detecting a channel can be further improved by checking the output of a coincidence detector coupled to the phase control loop. In this embodiment the coincidence detector outputs a logical true or false signal, depending on whether or not the synchronization phase control loop, while being closed, is synchronizing the horizontal oscillator with the incoming RF signal.

[0021] If the output is “true”, a valid channel frequency is detected and is stored in a non-volatile memory. If “false”, there is not detected a valid channel frequency, so this frequency is not stored.

[0022] These and other aspects of the invention will be apparent from and elucidated with reference to the accompanying drawings, in which:

[0023]FIG. 1 is a signal flow chart illustrating a prior art apparatus and method of synchronizing on-screen displays;

[0024]FIG. 2 is a timing sequence diagram for the signal flow chart of FIG. 1;

[0025]FIG. 3 is a signal flow chart illustrating an apparatus and a method according to the present invention;

[0026]FIG. 4 is a timing sequence diagram for the signal flow chart of FIG. 3; and

[0027]FIG. 5 is a flow chart illustrating one software implementation of the invention.

[0028] In FIG. 1, a known signal flow chart is shown in which an incoming radio frequency (RF) signal is received by an aerial 1 and passed to a television tuner 2. In known manner, the RF signal passes through a picture intermediate frequency phase-locked loop demodulator circuit (PIF PLL) 3 which demodulates the received signal to separate it into the constituent video signal and synchronizing signal. The video signal is passed to a video processor 4 and the synchronizing signal is applied to a synchronizing signal separator 5. The separator 5 may divide the horizontal synchronizing signal H.sync from the vertical synchronizing signal V.sync. The horizontal signal H.sync is applied to a first phase detector 6 and to a coincidence detection circuit 7, again in known manner. The output of the first phase detector 6 is filtered via a low pass filter and fed to a horizontal oscillator 8 which in turn supplies horizontal timing circuitry 10, to provide a horizontal display timing signal 11, a second phase reference signal (PH2 Ref), and a Burst-key signal BK.

[0029] The vertical signal V.sync is output to a vertical divider 12 and subsequently to a sandcastle generator 13, which also receives the Burst-key signal BK from the horizontal timing circuitry 10.

[0030] A second phase detection circuitry 14 receives the second phase reference signal PH2 Ref and the output signal from the sandcastle generator 13, which also provides the horizontal fly-back pulse. The output of the second phase detection circuitry 14 is filtered via a second low pass filter 15 and coupled to the horizontal drive circuitry 16 which generates a horizontal drive pulse HDP.

[0031]FIG. 2 is a timing diagram showing the correspondence between the coincidence status CS of the coincidence detection circuit 7 and the channel search status CSS. When the coincidence status CS changes from zero to one indicating that, while scanning the channel frequencies a channel has been found, the scanning of channel frequencies is paused during a time period Tp (indicated with status “1” in the channel search status CSS diagram). During this pause the accurate channel frequency is detected and subsequently stored during storing time Ts in a memory. Thereafter the channel search status becomes zero again, and the scanning of channel frequencies is resumed until a next channel is found.

[0032]FIG. 3 is a signal flow chart for an apparatus and a method according to the present invention. All of the known blocks illustrated in FIG. 1 are also present in this diagram but in addition extra stages, including a phase-locked loop (PLL) detection circuit 17, a line frequency detection circuit 18, and a first phase detector control circuit 19, are provided as described below.

[0033] The PLL detection circuit 17 determines whether the PIF PLL 3 is in a locked state. An output “1” indicates that it is in a locked state, whereas a “0” indicates that it is in an unlocked state.

[0034] The line frequency detection circuit 18 determines whether the incoming RF signal received by the aerial 1 has a video property, and thus whether a valid picture signal is being received. The line frequency detection circuit 18 detects the line frequency and, if it is present, it is likely that a TV broadcast signal is being received and it is thus desirable to store information related to this signal in the memory (not shown). Thus the detection circuit 18 outputs a logic “1”. If the line frequency is not detected, the detection circuit 18 outputs a logic “0”. The line frequency is actually 15.625 Hz for the European Standards. The line frequency may have another value which is depending on the broadcast system (for example, about 31 kHz or 32 kHz for HDTV). Instead of the line detection circuit 18 also other video property detection circuits can be used, indicating the presence of a video signal.

[0035] Further logic circuitry in the form of an AND gate 20, assesses the outputs of the PLL detection circuit 17 and the line detection circuit 18 and provides a control signal to the first phase detector control circuit 19 accordingly. This control signal can be supplied directly to the control circuit 19 or via a processor (not shown), which controls the execution of the method. Also the function of the AND gate 20 can be performed by the processor. Specifically, if the PLL is in lock and a video property is detected, the logic outputs of the detection circuits 17 and 18 will both be “1” and as a result a logic “1” is supplied to the first phase detector control circuit 19 to close the phase control loop 6, 8, 10 and enable the first phase detector to pass the horizontal synchronization signal H.sync for synchronization of the OSD display with the incoming signal.

[0036] On the other hand, if the PLL detection circuit 17 does not indicate a “Lock” or if there is no video property in the incoming signal, a logic “0” is supplied to the first phase detector control circuit 19 to open the phase control loop 6, 8, 10 and allow the horizontal oscillator 8 to free-run, thus avoiding interference to the OSD display by poorly received signals.

[0037] The switching timing of the following signals can be seen in FIG. 4:

[0038] the status signal Ls of the output of the line detection circuit 18,

[0039] the status signal PLL-S of the output of the PLL detection circuit 17,

[0040] the status signal PC supplied to the first phase detector control circuit 19,

[0041] the status signal CS of the output of the coincidence detection circuit 7, and

[0042] the signal indicating the channel search status CSS.

[0043] When both status signals LC and PLL-S are “1”, the first phase control circuit 19 receives the status signal PC equal to “1”. While status PC equals “1” the channel search is paused during the time Tp as indicated with status “1” of status signal CSS. During this time the control circuit 19 closes the phase locked loop comprising the first phase detector 6, the horizontal oscillator 8 and horizontal timing 10. This allows the coincidence detection circuit 7 to detect whether synchronization of the horizontal oscillator 8 with the incoming RF signal has been achieved (indicated with status “1” of status signal Cs). If yes, the presence of a channel is confirmed and the channel frequency is stored during storing time Ts. Thereafter the next channel is searched (indicated by status “0” of status signal CSS).

[0044]FIG. 5 provides a flow chart illustrating the software implementation covering the channel installation and comprising the following steps:

[0045]1. Channel search mode is initiated.

[0046]2. The first phase loop 6, 8, 10 is opened (meaning the horizontal oscillator 8 is free running) and the vertical divider 12 is set in the auto mode.

[0047]3. OSD information is generated (preferably for a full screen.).

[0048]4. The tuner starts to scan the channel frequencies for an incoming RF signal.

[0049]5. The RF signal is checked whether it comprises a line frequency signal, indicative of a video property.

[0050]7. If the line frequency is not detected, the next channel frequency is selected and step 5 repeated until a last channel frequency has been checked,

[0051]6. If the line frequency signal is detected, the channel frequency is kept constant for a predetermined pause time Tp.

[0052]8. The status of the PLL detection circuit 17 is checked

[0053]9. If the PLL detection circuit 17 is locked, the first phase detector 6 is switched on,

[0054] (If not, the program proceeds with step 7).

[0055]10. The channel frequency is kept constant (allowing the coincidence detector to reach a final value).

[0056]11. The coincidence detection circuit 7 assesses whether the horizontal oscillator 8 is synchronized with the incoming RF signal.

[0057]12. If yes, the frequency of the incoming RF signal is stored in a non-volatile memory (NVM) (not shown) and the next channel is selected in step 7. If no synchronization is detected the method proceeds immediately to step 7.

[0058]13. The program ends when all channels have been scanned.

[0059] The IC TDA957X H/N1 is a known TV signal processor which has a closed caption decoder with an embedded micro-controller. This processor can be applied to the apparatus and the method of the present invention and, for example, programmed in accordance with the flow chart of FIG. 5 in a manner which will be evident to a skilled person in this field. It should be noted that the invention could also be carried into effect by programming any one of several similar known processors or other circuitry and the invention is not intended to be limited to this illustrated circuit.

[0060] The invention is applicable to traditional television receivers and also to personal computers equipped with a television function.

[0061] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim. The word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. 

1. An apparatus for controlling synchronization of on-screen display information in an auto-search mode of a radio-frequency receiver (2) connected to scan an incoming signal for valid channel frequencies, the apparatus comprising: a detector (17) for supplying an output signal indicating whether an intermediate frequency demodulator is in an unlocked mode, which is the case if the incoming signal frequency does not correspond to a valid channel frequency, or in a locked mode, which is the case if the incoming signal frequency does correspond to a valid channel frequency; a video detector (18) for detecting a video property in the incoming signal; a synchronization phase control loop (6, 8, 10) which is closed if the video property is detected and the output signal indicates the locked mode; a memory for storing the frequency of the incoming signal as a valid channel frequency when the synchronization phase control loop (6, 8, 10) is closed; and a horizontal oscillator (8) connected to free run when the synchronization phase control loop (6, 8, 10) is open.
 2. An apparatus as claimed in claim 1 wherein the video property to be detected comprises a line frequency signal.
 3. An apparatus as claimed in claim 1, further comprising a coincidence detection circuit (7) to verify a coincidence detection status to confirm the presence of a valid channel frequency, the memory storing the frequency if the coincidence detection circuit (7) confirms the presence of a valid channel.
 4. A method of controlling synchronization of on-screen display information in the auto-search mode of a radio-frequency receiver (2), the method comprising the step of: a) initiating a channel frequency search mode; b) opening a synchronization phase control loop and setting a horizontal oscillator (8) to a free running mode; c) generating on-screen display information; d) scanning an incoming signal for valid channel frequencies; e) closing the phase control loop and pausing the scanning for a predetermined time if the incoming signal comprises a video property and an intermediate frequency phase-locked loop is locked; i) storing channel data while the phase control loop is closed. j) scanning for the next channel.
 5. A method as claimed in claim 4, wherein the video property to be detected is a line synchronizing signal.
 6. A TV signal processor comprising means for carrying out the method of claim
 4. 7. A television apparatus comprising the apparatus of claim 1 and a display device for displaying the on-screen display information. 